The present invention relates to a cold cathode type flat panel display, in particular, a spontaneously emitting type flat panel display using cold cathode electron sources.
As known well, a cold cathode type flat panel display is a display that comprises a phosphor film which is formed on a flat panel and emits by electron excitation and very small cold cathode electron sources arranged in a two-dimensional matrix form so as to be opposed to the phosphor film, and that has a function of irradiating the phosphor film with electron rays emitted from the electron sources to display an image on the panel. Displays using such very small cold cathode electron sources which can be integrated are generically named field emission displays (FEDs).
Cold cathode electron sources are roughly classified to field emission type electron sources and hot electron type electron sources. Examples of the former include a spindt type electron source, a surface conduction type electron source, and a carbon nano-tube type electron source. Examples of the latter include a metal-insulator-metal (MIM) type electron source, wherein a metal, an insulator and a metal are laminated, and a metal-insulator-semiconductor (MIS) type electron source, wherein a metal, an insulator and a semiconductor are laminated.
The MIM type electron source is disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-101965 (Patent Document 1) and Japanese Patent Application Laid-Open 2000-208076 (Patent Document 2). A structure of the MIM electron source and the operation principle thereof are shown in FIGS. 1 and 2.
FIG. 1 is a sectional structural view of an MIM type electron emitting element. In FIG. 1, bottom electrodes 11, made of, e.g., Al or Al alloy, are formed on an insulating cathode substrate 10 made of glass or the like so as to have a thickness of, e.g., 300 nm and be in a stripe form in the direction perpendicular to the surface of the drawing paper.
An interlayer insulator 14 (film thickness: e.g., 140 nm) for preventing the concentration of an electric field at edges of the bottom electrodes 11 and limiting or laying down an electron emission area, and a tunneling insulator 12 (film thickness: e.g., 10 nm) are formed.
Contact electrodes 15 and top electrode bus lines 16 are formed in a stripe form in the direction perpendicular to the bottom electrodes 11 (i.e., the right and left direction in the drawing paper), so as to avoid the electron emission area E. The electron emission area E corresponds to top electrodes 13 on the tunneling insulator 12. The top electrodes will be described in detail later.
The contact electrodes 15 are made of a metal film having a strong adhesive force to the cathode substrate 10 or the interlayer insulator 14, for example, a high melting point metal such as W (tungsten) or Mo (molybdenum) or a silicon compound thereof (silicide), so as to have a film thickness of, e.g., about 10 nm.
The top electrode bus lines 16 are bus lines which can be connected to the top electrodes 13, which will be detailed later, at a low resistance and are made of an Al—Nd alloy film, so as to have a thickness of 200 nm. In order to prevent the snapping of the top electrodes 13, which will be detailed later, it is desired that a metal film as an underlying layer 15A for the contact electrodes is made as thin as possible.
On the top electrode bus lines 16, the interlayer insulator 14 and the cathode substrate 10 except the electron emission area E, a surface protection film 17 is formed, which is an insulator film made of, for example, intrinsic silicone, SiO2, glass (such as phosphor doped glass or boron doped glass) , Si3N4 (nitride) , Al2O3 (alumina) or polyimide. For reference, in the case of using Si3N4, the film thickness thereof is from 0.1 to 1 im.
The tunneling insulator 12 is covered with top electrodes 13. The top electrodes 13 have a three-layer structure composed of a lower layer made of Ir (iridium), which is good in heat resistance, an intermediate layer made of Pt (platinum) and an upper layer made of Au (gold), which is good in electron emitting efficiency, and are applied onto the tunneling insulator 12 in a thin film forming step using, for example, sputtering.
In this thin film forming step, the layer of the top electrodes 13 is simultaneously deposited on the surface of the surface protection film 17. As shown in FIG. 1, however, the layer of the top electrode bus lines 16 retreats inwards from end faces of the surface protection film 17 so that the surface protection film 17 is made into the form of eaves. Consequently, a metal film 13′ on the surface protection film 17 is electrically insulated from the top electrodes 13 on the tunneling insulator 12.
When a voltage Vd is applied between the bottom electrodes 11 and the top electrodes 13 of the MIM type electron emitting element having a structure as described above in vacuum, electrons, in the bottom electrodes 11, having an energy level near the Fermi level penetrate through a potential barrier by tunneling phenomena, so as to be injected into the conduction band of the tunneling insulator 12 and the top electrodes 13. As a result, hot electrons are generated. Among these electrons, electron having a kinetic energy equal to or more than the work function φ of the top electrodes 13 are emitted into the vacuum.
A document related to such a technique is Japanese Patent Application Laid-Open No. 2001-83907 (Patent Document 3).
FIG. 46 is a sectional view illustrating an outline of a display panel in the prior art. As illustrated in this figure, in order to use the above-mentioned MIM type electron sources to construct a display device, the cathode electrode 10 wherein the electron sources having the structure illustrated in FIG. 1 are arranged in a matrix form and an anode substrate 110 wherein phosphor film pieces 111 are arranged in a matrix form so as to correspond to the electron source elements of the cathode substrate 10 are adhered through a glass frame member 116 made of glass or the like by junction based on frit glass 115, thereby making an inner space 118 into vacuum. In this way, a display panel (flat panel display) 120 is yielded. As will be described in more detail later, the anode substrate 110 is made of a light-transmitting flat panel, and the whole of a single surface of the anode substrate 110, including the surfaces of the phosphor film pieces 111, is covered with a conductive film (called a metal back) 114.
When the diagonal size of the display panel 120 is more than 5 inches in this case, it is necessary to insert spacers 30 made of an insulator material, as reinforcing materials, at intervals of several centimeters into the inner space (vacuum atmosphere) of the panel in order to keep the atmospheric pressure.
A part of electrons emitted from the electron source elements collides with these spacers 30, so that the spacers 30 are charged up. Near the charged spacers, the orbit of the electrons is curved so as to cause a phenomenon that an image is distorted. In order to prevent this phenomenon, a slight conductivity is given to the surface of the spacers 30 by means of a high-resistance film made of tin oxide, a mixed crystal thin film made of tin oxide and indium oxide, a metal film, a semiconductor film or some other film. In this way, the electrification of the spacer surfaces is removed.
It is therefore necessary to connect the spacers 30 electrically to the metal back 114 on the side of the anode substrate 110 and the top electrodes 13′ on the surface protection film 17 on the side of the cathode substrate 10. The top electrodes 13′ for giving grounding voltage on the side of the cathode substrate 10 have a thickness of 10 nm or less and further have a weak adhesive force to the surface protection film 17; therefore, when pressure from the spacers is applied to the top electrodes 13′, the snapping or breaking down thereof is easily caused. In order to prevent this, it is necessary to set third bus lines independently of the data lines (the top electrode bus lines 16 and the scan lines (the bottom electrodes 11), as ground lines 18 for the spacers 30, on the surface protection film 17.
However, in the case of adopting the three-layer line structure wherein the data lines 16, the scan lines 11 and the third bus lines independently thereof are set on the side of the cathode substrate 10 as described above, the production process thereof unavoidably becomes longer than the production process including the formation of two-layer bus lines. As a result, problems of a drop in the yield or an increase in the production costs are caused.